1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, particularly to a semiconductor integrated circuit device suitable for a high speed and low voltage operation, and a storage medium on which a cell library is stored.
2. Description of the Prior Art
There are widely used MOSFETs each having features of a high integration density and low consumption power, in semiconductor integrated circuit devices currently fabricated. A MOSFET has a threshold voltage by which ON-OFF characteristics of the FET are determined. In order to increase a drive ability and improve an operating speed in a circuit, there is a need for setting a threshold voltage to a low value.
However, when a threshold voltage is set to an excessively low value, there arise problems that an MOSFET cannot perfectly be turned off due to subthreshold characteristics (tailing characteristics) of the MOSFET, a subthreshold current (hereinafter xe2x80x9cleakage currentxe2x80x9d is used) is increased and thereby consumption power is very large, as described in 1993 Symposium on VLSI Circuits Digest of Technical Papers, pp. 45-46 (May) 1993.
Generally, in order to increase a threshold voltage of a MOSFET, there have been employed methods in which a thicker gate oxide film is adopted or a higher impurity density is provided under a gate oxide film. In other words, in designing a semiconductor integrated circuit device which is constructed of MOSFETs, a desired operating frequency and consumption power are first considered and a threshold voltage is then determined, which is finally followed by determination of process conditions in semiconductor fabrication.
MOSFETs in a semiconductor integrated circuit device generally have a constant threshold voltage. According to an invention made in recent years, however, there has been proposed a semiconductor integrated circuit in which a substrate bias voltage is changed according to an operating state, standby or active, and thereby a threshold voltage of a MOSFET is controlled, as described in IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 166-167,1996.
According to the published Unexamined Japanese Patent Application No. Hei 8-274620, there has been proposed a technique that in the case where a semiconductor circuit is constructed with a plurality of functional blocks, a substrate bias voltage is independently selected in each functional block and a MOSFET with a low threshold voltage is provided in a block in whose operation a high speed is important, while a MOSFET with a high threshold voltage is provided in a block in whose operation a high speed is not important.
There has been a further proposal in IEEE Journal of Solid-State Circuit, Vol. 30, No. 8, pp.847-854, August 1995 that a power source supply line and a pseudo-power source supply line are provided in a circuit and a switching MOSFET is disposed therebetween, wherein a main circuit is supplied with a source voltage from the pseudo-power source supply line and in a standby state, the main circuit is not supplied with the source voltage by turning off the switching MOSFET, so that low consumption power is realized. In the article, there has also been proposed that the switching MOSFET has a higher threshold voltage as compared with MOSTETs constituting the main circuit in order that the switching MOSFET is kept the ON state in the active operating condition, while acting no switching.
As described above, there has been proposed in the prior art that a threshold voltage of a MOSFET is controlled by changing a substrate bias voltage according to operating states, standby or active; or a substrate bias voltage is independently selected in each functional block and a MOSFET with a low threshold voltage is provided in a block in whose operation a high speed is important, while a MOSFET with a high threshold voltage is provided in a block in whose operation a high speed is not important.
Besides, there has been proposed in the prior art that a high threshold voltage is used in a specific MOSFET for which a switching speed is not required in an operation. However, in the method that threshold voltages of MOSFETs are uniformly increased in a standby state and those are again uniformly decreased in an active operating state, increase in consumption power due to leakage current cannot be avoided in order to secure a high speed operation in the active operating state. Besides, the inventors of the present invention has discovered through a study conducted by them that there is actually present a case where a necessary operating speed is different in a different logic gate among logic gates even in the same functional block.
FIG. 11 shows a frequency distribution of delays in paths between flip-flops in a semiconductor integrated circuit operated at 100 MHz. The abscissa is used for plotting values of delays in paths and the ordinate is assigned to values of the number of paths respectively corresponding to the delay values. In order to operate at 100 MHz, a frequency distribution of delay values in the entire paths is necessary to be confined within a range less than a delay value of 10 nsec like the frequency distribution (1) shown in the figure. When an operating speed of the semiconductor integrated circuit is operated at 125 MHz, the entire paths has to fall in a frequency distribution less than a delay value of 8 nsec. To match such a condition, according to the prior art, there was two choices; one is to change process conditions and the other is to uniformly lower threshold voltages of MOSFETs constituting a circuit by changing a substrate bias source.
As a result, for example, a distribution of delay values is changed like the frequency distribution (2) of FIG. 11. In this case, however, consumption power by a leakage current is increased and there arises a risk that a required condition posed on consumption power is not met. Besides, in the case where consumption power is required to be further reduced, according to the prior art, there was again two choices; one is to change a process condition and the other is to uniformly increase threshold voltages of MOSFETs constituting a circuit by changing a substrate bias source. As a result, a distribution of delay values is changed like the frequency distribution (3), for example. That is, an operating speed is lowered and thereby 100 MHz cannot be realized.
Consequently, a compromise must be accepted determining whether an operating speed is attached with a grater importance or lower power consumption is chosen with priority.
It is an object of the present invention to solve the problems which the prior art has had. That is, it is an object of the present invention to provide a semiconductor integrated circuit device in which a harmony between increase in consumption power due to a leakage current and a operating speed is properly achieved, and thereby, not only is increase in consumption power by a leakage current of a MOSFET suppressed but a high speed operation is achievable in an active operation.
It is another object of the present invention to provide a storage medium on which there is stored a cell library necessary for designing a harmony between increase in consumption power due to a leakage current and a operating speed in a suitable manner.
It is a further object of the present invention to provide a designing method of a semiconductor integrated circuit device for designing a harmony between increase in consumption power due a leakage current and a operating speed in a suitable manner.
An essential point of the present invention for solving the above problems is to construct a semiconductor integrated circuit device using MOSFETs with different threshold voltages even in the same functional block in a given operating condition, for example in an active operating condition in which a high speed is required.
In particular, a first feature of a semiconductor integrated circuit device of the present invention is that the semiconductor integrated circuit device is constructed, in order to satisfy a requirement for an operating frequency, in such a manner that in a plurality of signal paths of the circuit, a path which has a margin in delay is constructed with MOSFETs each with a high threshold voltage in each of which an operating speed is low but a leakage current is small, whereas a path which has no margin in delay is constructed with MOSFETs each with a low threshold voltage in each of which a leakage current is large but an operating speed is high, in consideration of time, that is a delay, required for a signal to be transmitted along a signal path.
A second feature of a semiconductor integrated circuit device of the present invention is that when, in a signal path in the semiconductor integrated circuit device, if the path is constructed of only MOSFETs each with a high threshold voltage, a delay is large and a requirement for an operating frequency cannot be satisfied, but if the path is constructed of only MOSFETs each with a low threshold voltage, a margin arises in delay and consumption power due to a leakage current is uselessly increased, then MOSFETs each with a low threshold voltage and MOSFETs each with a high threshold voltage are mixed in a proper manner along the signal path and thereby, a delay which satisfies a requirement for an operating frequency is secured and at the same time a leakage current is suppressed to a minimum.
A third feature of a semiconductor integrated circuit device of the present invention is that in the case where, in the semiconductor integrated circuit device, when a construction in which a signal path from one starting node is branched at a node and then branches lead to a plurality of node contains a mixture of MOSFETs each with a low threshold voltage and MOSFETs each with a high threshold voltage in a proper manner as described above, more of MOSFETs each with a low threshold voltage are used along the path from the starting node to the branching node in order to minimize the use of MOSFETs each with a low threshold voltage in number, on the other hand, when a construction in which signal paths from a plurality of starting nodes are converged at a node and then a single signal path leads to one final node contains a mixture of MOSFETs each with a low threshold voltage and MOSFETs each with a high threshold voltage in a proper manner as described above, more of MOSFETs each with a low threshold voltage are used along the path from the converging node to the final node in order to minimize the use of MOSFETs each with a low threshold voltage in number.
First means for constructing a semiconductor integrated circuit with MOSFETs with different threshold voltages according to the present invention is that an impurity density of a semiconductor substrate under a gate oxide film of a MOSFET is changed, second means of the constructing the semiconductor integrated circuit is that a bias voltage value supplied to a substrate of the MOSFET is changed, third means is that a thickness of a gate oxide film of the MOSFET and fourth means is that a gate length of the MOSFET is changed.
A feature of the present invention is that MOSFETs with different threshold voltages are constructed with combinations of the four means.
A feature of the present invention is that, in the second means for constructing MOSFETs with different threshold voltages, a plurality of insular well regions which are insulated from each other are constructed in order to change a bias voltage value supplied to the substrate of a MOSFET and MOSFETs with different threshold voltages are disposed on different well regions.
A feature of the present invention is that, in order to dispose MOSFETs with different threshold voltages on different well regions, logic gates are arranged one dimensionally in one line and a plurality of rows of logic gates are arranged in directions perpendicular to the one line so as to dispose logic gates two dimensionally, wherein logic gates constituted of MOSFETs each with the same threshold voltage are arranged on the same row and MOSFETs each with the same threshold voltage are constructed on the same well region disposed along the row, and wherein a bias source is supplied by a wire in the same direction as that of a row.
A feature of the present invention is that when logic gates, which are constructed with MOSFETs each with the same threshold voltage, are arranged on one row and the logic gates are fabricated on the same well region disposed along the one row, a plurality of rows of logic gates which are arranged an adjacent manner to one another own commonly one well region among them if the plurality of logic gates are constructed with MOSFETs each with the same threshold voltage.
A feature of the present invention is that a storage medium on which there is stored a cell library used for designing the semiconductor integrated circuit is registered with at least two kinds of cell, which has the same function and the same size, but which are constructed with MOSFETs with different threshold voltages, and which, thereby, have different delays and different consumption power.
A feature of the present invention is that there is adopted a designing method for the semiconductor integrated circuit device which uses the storage medium on which the cell library is stored and comprises the steps of: calculating a delay of a signal path; and assigning to a logic circuit one cell selected among at least two kinds of cells constructed of switching elements, which have the same function and the same size, but which have different threshold voltages, using a calculation result by the step of calculating a delay of a signal path.
A feature of the present invention is that there is adopted another designing method for the semiconductor integrated circuit device which uses the storage medium on which the cell library is stored and comprises the steps of: designing a logic circuit using only cells constructed of switching elements each with a high threshold value; calculating a delay of a signal path; and replacing part of cells of the logic circuit designed using only cells constructed of switching elements each with a high threshold value by a cell constructed of switching elements each with low threshold value, each of which has the same function and the same size.
A feature of the present invention is that in application, a semiconductor integrated circuit comprises a signal path containing a plurality of circuits each of which holds a state of a signal, such as a latch circuit, a flip-flop circuit, a signal output terminal or a signal input terminal, wherein there are provided a plurality of transistors with different threshold values in paths between circuits. A feature of the present invention is that in application, a semiconductor integrated circuit comprises a plurality of first circuits controlled by a clock signal in a signal path and a second circuit including a plurality of transistors with different threshold values inserted between first circuits.
As a designing concept, a designing method of the present invention is a designing method for a semiconductor integrated circuit device in which a plurality of first circuits controlled by a clock signal are included in a signal path and a second circuit constructed of a plurality of transistors with different threshold values are inserted in paths between first circuits, wherein a threshold value of each of transistors constituting the second circuit is set so that a signal delay time between first circuits does not exceed a given target value.
That is, it is unavoidable that there exists a path which has the largest delay time, which determines an overall operating speed among paths between a plurality of first circuits. However, a delay time of the path can be smaller and an operating frequency of the entire circuit can in a proper manner be improved by using high speed transistors each with a low threshold value in such a path having a large delay time.